1. Field of the Invention
The present invention relates, in general, to a semiconductor package and packaging method using a flip-chip bonding technology and, more particularly, to a semiconductor package and packaging method, in which a microelement array of a micro-device, for example, a micromirror array of a light modulator comprising micromirrors that are hyperfine elements, is sealed from the outside of the micro-device using a flip-chip bonding technology, so that the microelement array is protected from the outside.
2. Description of the Related Art
In the related art, various methods of packaging semiconductor devices or microoptical devices, which are designed and produced with hyperfine precision, have been proposed.
As an example of conventional semiconductor packaging technologies, U.S. Pat. No. 6,303,986 discloses a method and apparatus for sealing a hermetic lid to a semiconductor device.
As shown in FIG. 1, a conductive ribbon 100 having a metallic conductive/reflective mirror 102 is formed over an upper surface of a semiconductor substrate 104, with an air gap 106 defined between the ribbon 100 and the substrate 104. A conductive electrode 108 is placed under the ribbon 100 so that the air gap 106 is defined between the ribbon 100 and the conductive electrode 108. The conductive/reflective mirror 102 extends beyond the region of the mechanically active ribbon 100 and is configured as a bond pad 112 at its distal end. The semiconductor device is also passivated with an insulating protective layer 114 which does not cover the bond pad 112 or the ribbon structure 100 and 102. Control and power signals are coupled to the semiconductor device using conventional wire bonding structures 116.
Furthermore, a hermetic lid 122 made of a light transmissive material is joined to the semiconductor device. The lid 122 is formed to a size appropriate to fit concurrently over lid sealing regions 118, with a first solderable material 120 formed in a ring on the lid sealing regions 118 and a second solderable material 124 formed in a ring surrounding the periphery of one surface of the lid 122. A solder 126 is deposited onto the solderable material 124 so that the lid 122 is joined to the semiconductor device.
In the semiconductor packaging technique disclosed in the above-mentioned U.S. patent, the conductive electrode pattern for driving the semiconductor device passes through the hermetic sealing layer. Thus, the insulating protective layer must be provided in the semiconductor device, and thereby complicates the construction of the semiconductor device.
U.S. Pat. No. 5,293,511 discloses a method of packaging a semiconductor device. This U.S. patent discloses that anodic bonding, eutectic bonding, glass-frit bonding, soldering and epoxy bonding may be used to bond a cover to a base substrate.
However, the conventional semiconductor packaging techniques are problematic in that an excessive number of processes must be executed during a packaging process. Thus, the packaging process is complicated, and may result in an excessive number of defective products and an increase in production costs of the semiconductor packages.
Furthermore, the above-mentioned conventional semiconductor packaging techniques cannot package semiconductor devices as a wafer, but package the individual semiconductor devices one by one, thus complicating the packaging processes. Therefore, a reduction in production costs of the packages cannot be accomplished.
In addition, in the above-mentioned conventional semiconductor packaging techniques, a wire-bonding process must be executed prior to a flip-chip bonding process, which is capable of increasing the bonding process efficiency.